V
Visla Hardware
Portal R&D
πŸ’€ CSCLK (UART sleep)

A7670E Β· CSCLK (UART sleep)

Misurato su: πŸ“¦ LilyGO T-A7670 R2 (board completa, non chip nudo)
πŸ“… 2026-05-28 13:23:48 Β· πŸ”‹ FNB58 USB-C tester (Bluetooth, 4 Hz sample) Β·πŸ“Ά β€” (modem off/sleep)

Sleep UART del modem (AT+CSCLK=1 + DTR HIGH): UART sospesa, <1 mA.

← Chip A7670E
Samples
445
Duration
111s
I min
13.9 mA
I avg
19.83 mA
I peak
94.2 mA

πŸ“ˆ Consumo nel tempo

300 punti (downsampled da 445)

πŸ“‹ Report bench